Shared memory computers comprising a plurality of CPUs (Central Processing Units) and which share physical memories between CPUs are being widely used. Pursuant to the improvement in the storage density of memories resulting from the advancement in semiconductor technology and the emergence of multi-core processors comprising a plurality of processor cores on the same processor chip, the memory capacity and number of CPUs that can be mounted on a single computer are increasing. In this kind of computer, technology for running a plurality of different OSs on the same computer has been put into practical application.
When running a plurality of different OSs on the same computer, resources such as the CPU, memory, and I/O (Input/Output) device of the computer are shared between OSs or logically divided and occupied by one OS based on technologies such as virtualization and logical partitioning. Examples of an I/O device include, for example, an HBA (Host Bus Adapter) for coupling the computer to a storage apparatus, and an NIC (Network Interface Card) for coupling the computer to a network. Patent Literature 1 discloses technology for coupling these I/O devices to a plurality of CPUs in the same computer. Moreover, Patent Literature 2 discloses technology for sharing, among a plurality of virtual computers in a plurality of physical computers, an I/O device corresponding to the SR-IOV (Single Root I/O Virtualization) standard which has been standardized by PCI-SIG (PCI Special Interest Group).
As the communication methods between OSs running on the same computer, in addition to the method of performing communication via an I/O device as with the case where the respective OSs are running on independent computers, there is the method of performing communication via a physical memory area of the shared memory which can be shared and used between OSs. Furthermore, in cases where the respective OSs are occupying and using a CPU, there is also the method of performing communication by using an inter-processor interrupt from the CPU which is executing the OS of the communication source to the CPU which is executing the OS of the communication destination. Patent Literature 3 discloses technology of performing inter-processor communication by using a shared memory and socket communication.